I. Field of the Disclosure
The technology of the disclosure relates generally to timing of one or more signal paths in a multiple voltage domain circuit. The technology of the disclosure also relates to timing of one or more signal paths in memory circuits.
II. Background
Circuits are increasingly being designed with conservation of power in mind. This is particularly the case for portable electronic devices that are battery-powered. Common examples include mobile phones and laptop computers among others. Increased power consumption undesirably results in faster battery drain and shorter battery life. One method of conserving power is to lower the operating frequency of the circuit according to the active power equation P=CV2f. However, reducing operating frequency results in lower circuit performance (i.e., speed). Another method of conserving power is to lower the operating voltage level since generally, active power reduces quadratically for a given reduction in operating voltage level. However, lowering the operating voltage level in a circuit lowers speed performance, which may also be undesirable. Further, certain cells or components of a circuit may have a minimum operating voltage below which they will not operate properly.
To address the tradeoff between performance and power consumption, multiple operating voltage domains (“voltage domains”) are increasingly being provided in circuits. Circuit paths are provided which pass through the multiple voltage domains to provide different operating voltages to different components of a circuit. Providing multiple voltage domains allows a lower voltage domain to provide power to components that do not require minimum voltage levels to conserve power. Components that either have a minimum operating voltage level for proper operation or provide critical paths where performance cannot be sacrificed may be powered by the higher voltage domain. Providing multiple voltage domains also allows the lower voltage domain to be scaled-down to conserve power during a power conservation mode, or scaled-up to provide for increased performance (i.e., hyper-performance), without affecting the operation of the components in the higher voltage domain.
Examples of circuits where multiple voltage domains are commonly employed are memory circuits and memory systems. One example is static random access memory (SRAM). SRAM may be used on cache memory. SRAM cells have a minimum operating voltage level to retain stability and properly retain data. Further, the minimum operating voltage is higher to address minimum operating voltage level issues for SRAM cells provided in deep sub-micron geometries less than one-hundred (100) nanometers (nm), such as sixty-five (65) nm and forty-five (45) nm geometries as examples. One example of an SRAM system employing multiple voltage domains is illustrated in FIG. 1. Therein, an exemplary SRAM memory system 10 (referred to as “memory system 10”) is provided. Input lines 12 and output lines 14 are coupled to the memory system 10. The input lines 12 and output lines 14 carry signals to allow command and data communication between the memory system 10 and other system components that write or read data to and from an SRAM cell array 16, which operates as a mass memory device. A control system 18 controls the operation of the SRAM cell array 16.
The memory system 10 contains two signal paths, labeled “access path” 20 and “sense path” 22. The access path 20 transfers access signals from the control system 18 to word line drivers 26 (i.e., row selector), possibly through intermediary logic 24. In response, the word line drivers 26 activate a specific row of memory cells within the SRAM cell array 16 in response to address information from the control system 18. The address information identifies a specific row in the SRAM cell array 16 to be selected. The row may be selected for either a read or write operation. In response, data from the selected row in the SRAM cell array 16 is placed on bit lines 28. In order to read the data placed on the bit lines 28, the control system 18, and possibly intermediary logic 30, communicates a sense signal to sense amplifiers 32 to perform a read on the bit lines 28. The sense amplifiers 32 sense the data from the bit lines 28 and place the data on output lines 14.
In the memory system 10, the timing for signals to traverse the access path 20 and the sense path 22 are compatible. Specifically, the memory system 10 is designed so that a sense pulse signal communicated by the control system 18 over the sense path 22 does not cause the sense amplifiers 32 to sense data on the bit lines 28 before access signals are communicated by the control system 18 over the access path 20 to cause the SRAM cell array 16 to assert data on the bit lines 28. Otherwise, the sense amplifiers 32 will sense data on the bit lines 28 before the SRAM cell array 16 has asserted valid data on the bit lines 28. It is acceptable for access signals communicated over the access path 20 to reach the SRAM cell array 16 before sense signals reach the sense amplifiers 32 over the sense path 22. In this scenario, data on the bit lines 28 will be present before the sense amplifiers 32 are activated to sense data on the bit lines 28. The delay of the access path 20 in the memory system 10 provides the minimum delay for which sense signals should traverse the sense path 22 to the sense amplifiers 32.
The memory system 10 of FIG. 1 operates in a higher voltage domain VH provided at the minimum voltage level VMIN sufficient to provide stable operation and data storage in the SRAM cell array 16. The input lines 12 and output lines 14 come from components that are provided in a lower voltage domain VL. In this regard, one or more level shifters 34 are provided to convert the signals on the input lines 12 from the lower voltage domain VL to the higher voltage domain VH. Signals communicated from the sense amplifiers 32 to the output lines 14 may be converted from the higher voltage domain VH to the lower voltage domain VL with or without one or more level shifters 36.
It may be desirable to power certain components or portions of the memory system 10 in a lower voltage domain VL. Providing multiple voltage domains in a circuit allows scaling of a voltage domain to conserve power without affecting the operation of the components powered by other voltage domain(s). However, because different voltage domains operate independently, the voltage level differential between them can vary. Variations in voltage levels between different voltage domains can cause discrepancies in delays of signal paths in a circuit. Large discrepancies may render the circuit non-functional.